(a) Field of the Invention
The present invention relates to a semiconductor device having a silicide structure and, more particularly to an improved silicide structure using a semi-insulating polycrystalline silicon film. The present invention also relates to a method for manufacturing the same.
(b) Description of the Related Art
Recently, a shallow junction structure is a key technology in a diffused region of small sized and high density semiconductor devices. In the shallow junction structure, some problems are reported in connection with the contacts between diffused regions and overlying metallic interconnects.
FIGS. 1A to 1D show a semiconductor device in consecutive fabrication steps thereof, which is proposed for solving the above mentioned problems by Y. Taur, S. Cohen, S. Wind et al., in "International Electron Device Meeting Technical Digest (IEDM)", pp901, 1192.
In FIG. 1A, a field oxide film 302 is formed on a silicon substrate 301, followed by formation of an oxide film and a polycrystalline silicon (polysilicon) film. After an electron beam (EB) exposure, a reactive ion etching using a HBr/Cl.sub.2 etching gas is conducted at a high selectivity between the silicon substrate and the silicon oxide film to form a gate structure including a gate oxide film 303 and a gate polysilicon film 304, thereby obtaining 0.1 micron-order gate length for a MOSFET.
Subsequently, Sb ions are introduced to the surface portions of the silicon substrate to make the surface portions of the silicon substrate 301 amorphous, followed by ion-implantation with BF.sub.2 ions 316 having a low acceleration energy, and forming p+ extensions 317 having a depth as low as 50 to 70 nanometers (nm), as shown in FIG. 1A. The p+ extension 317 functions for alleviating difficulties in forming contacts between the diffused regions and overlying metallic interconnects as well as reducing the contact resistance therebetween.
Thereafter, as shown in FIG. 1B, an oxide film is deposited, followed by etch-back thereof to form a side-wall 305. A selective ion-implantation of silicon surface with impurity ions 318 is then effected to form source/drain regions 319 having a depth larger than the depth of the p+ extensions 317. A blanket Ti film 310 is then deposited on the entire surface by sputtering, as shown in FIG. 1C.
Thereafter, a sintering is conducted to form a TiSi film 311 at the interface between the source/drain region 319 and the Ti film 310. An interlayer dielectric film 309 is then deposited, followed by dry-etching thereof to form via-holes (through-holes). Sputtering and subsequent etching of AlSiCu, for example, provide metallic interconnects 312 in the semiconductor device, as shown in FIG. 1D.
In the proposed process, the shallow p+ extensions 317 enables fabrication of 0.1-micron order small-sized transistors with an enough process margin for the contacts between the heavily doped regions 319 and the metallic interconnects 312.
However, there is a possibility that the doped impurity ions diffuse in the lateral direction as well as the vertical direction during the thermal treatment for activation of the impurity ions in the heavily doped source/drain regions 319. The lateral diffusion generally demands a large thickness of the side-wall 305 in the gate structure for assuring the presence of the shallow p+ extensions 317, which hinders a smaller gate length in the gate structure. Moreover, the silicide structure employed for reducing the resistance of the diffused regions 319 and metallic interconnects 312 tends to cause a leakage current flowing between the gate electrode and the source/drain regions due to an inaccurate positioning of etching or diffusion.
FIGS. 2A to 2D show, similarly to FIGS. 1A to 1B, a second conventional fabrication process, proposed by H. Kotaki, M. Nakano, Y. Takegawa et al. in "International Electron Device Meeting Technical Digest (IEDM)", pp839, 1993. A field oxide film 402 is formed on a silicon substrate 401, followed by formation of gate oxide film 403, gate polysilicon film 404 and side-wall 405. The resultant wafer is introduced into a Load-Lock chamber of a LPCVD equipment, wherein N.sub.2 gas having a dew point of -100.degree. C. flows, while controlling the equipment so that a native oxide film or water molecules are not attached to the surface of the wafer.
A Si film 420 is then deposited thereon by using a SiH.sub.4 gas at a substrate temperature of 620.degree. C., as shown in FIG. 2A. In this step, a Si epitaxial layer is formed on the surface of the silicon substrate 401 due to the clean surface thereof, whereas a polysilicon film is formed on the oxide films 402 and 405.
A selective etching for the polysilicon film by using an etchant containing HNO.sub.3 and CH.sub.3 COOH leaves the elevated Si epitaxial layer 421 formed on the surface of the silicon substrate 401, as shown in FIG. 2B. An ion-implantation with impurity ions 418 and subsequent activation heat treatment are then conducted to provide a shallow diffused layer 422, followed by sputtering to form a Ti film 410 thereon, as shown in FIG. 2C.
A TiSi film 411 is then selectively formed on the surface of the Si epitaxial layer 421, followed by deposition of a blanket interlayer dielectric film 409 and subsequent selective dry-etching thereof to form via-holes. Then, sputtering and subsequent patterning of a metal such as AlSiCu is effected to form metallic interconnects 412 having via-plugs formed in the via-holes, as shown in FIG. 2D.
In the second conventional process as described above, the elevated Si epitaxial source/drain regions 421 provide advantages of suppression of the transistor short-channel effect in the shallow source/drain regions, reduction of resistance in the diffused regions and via-plugs due to the metallic silicide layer, and a larger process margin between the heavily doped source/drain regions and the metallic interconnects.
In a small-sized semiconductor device formed by the second conventional technique, the epitaxial step for the elevated epitaxial source/drain regions involves contamination at the interface between the elevated epitaxial regions and Si substrate in a small-sized semiconductor device formed on a larger wafer, which requests a surface treatment at the interface between the epitaxial layer and the silicon substrate during the growth step. The second conventional process also requests a high selectivity between the polysilicon film and the monocrystalline silicon substrate, which is difficult to achieve in mass production.